Exemplary embodiments of the present invention relate to semiconductor memory devices, and more particularly, to a repair analysis device and method for calculating a repair solution by using information about a fault cell detected in a memory device.
In the early stage of semiconductor memory industry, a wafer with a larger number of original good semiconductor dies with no defective cell could be produced in a semiconductor fabrication process. However, as the memory capacity has increased, it has become difficult to fabricate a memory chip without any fault cell.
Accordingly, a method for replacing a fault memory cell with a spare memory cell (i.e., a redundancy memory cell) has been proposed. In order to replace a fault memory cell with a redundancy memory cell, an external equipment has been used to calculate a path to the replacement. More recently, however, such a repair circuit has been installed in a memory chip.
Three main parameters to be considered for a memory self-repair circuit may be an area overhead, a repair rate, and an analysis speed of a repair circuit. The area overhead is a parameter connected directly with the semiconductor chip fabrication cost. The repair rate is an important parameter connected with the yield of the semiconductor chip. The analysis speed of a repair circuit may also be regarded as a parameter connected directly with the semiconductor chip fabrication cost, because it is proportional to a test time.
A built-in self repair analyzer (CRESTA) is disclosed in a prior art 1 (T. Kawagoe, J. Ohtani, M. Niiro, T. Ooishi, M. Hamada, and H. Hidaka, “A built-in self repair analyzer (CRESTA) for embedded DRAMs” in Proc. Int. Test Conf., pp. 567-574, October 2000). The CRESTA of the prior art 1 is a relatively widely known redundancy analysis operation circuit. Among the conventional redundancy analysis operation circuits, the CRESTA of the prior art 1 has the highest repair rate (a repair rate of 100% if a repair solution is present) and the highest redundancy analysis operation speed. With respect to a redundancy sequence available by a given redundancy circuit, all cases are implemented using an auxiliary operation circuit, and thus analysis operations may be simultaneously performed on all the cases. Accordingly, the repair rate and the analysis operation speed can be optimized. However, the CRESTA of the prior art 1 is to install separate auxiliary operation circuits for all the cases, respectively. Therefore, the CRESTA of the prior art 1 exponentially increases the area overhead if the number of cases of a redundancy sequence increases due to an increase in the number of redundancy cells.
An “intelligent solve first” method is disclosed in a prior art 2 (P. Ohler, S. Hellebrand, and H.-J. Wunderlich, “An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy” in Proc. European Test Symposium (ETS), pp. 91-96, May 2007). The “intelligent solve first” method of the prior art 2 is a relatively recent method based on a branch-and-bound algorithm. The “intelligent solve first” method of the prior art 2 excludes a must-repair line from a binary tree structure, thereby securing a relatively low area overhead and the optimal repair rate. However, the “intelligent solve first” method of the prior art 2 excessively increases a redundancy analysis operation time if the number of faults (i.e., cells) increases or the distribution thereof becomes complicated. Also, the “intelligent solve first” method of the prior art 2 cannot secure the optimal repair solution.
An essential spare pivot (ESP) method is disclosed in a prior art 3 (C.-T. Huang, C.-F. Wu, J.-F. Li, and C.-W. Wu, “Built-in Redundancy Analysis for Memory Yield Improvement, IEEE Trans. Reliability, vol. 52, pp. 386-399, December 2003). The ESP method of the prior art 3 stores only core fault addresses instead of a fault bit map in order to reduce the area overhead. A fault address collecting process is performed during a test process, thus increasing the analysis speed of a self-repair circuit. However, a register capacity for storing fault addresses is insufficient, thus failing to accurately reproduce a fault phenomenon. Therefore, the ESP method cannot secure the optimal repair solution and analysis result.